Figure 4-9. ai/sampleclock and ai/convertclock, Other timing requirements, Other timing requirements -18 – National Instruments NI USB-621x User Manual
Page 44
Chapter 4
Analog Input
4-18
ni.com
Figure 4-9 shows the relationship of ai/SampleClock to ai/ConvertClock.
Figure 4-9. ai/SampleClock and ai/ConvertClock
Other Timing Requirements
The sample and conversion level timing of M Series devices work such that
clock signals are gated off unless the proper timing requirements are met.
For example, the device ignores both ai/SampleClock and ai/ConvertClock
until it receives a valid ai/StartTrigger signal. Once the device recognizes
an ai/SampleClock pulse, it ignores subsequent ai/SampleClock pulses
until it receives the correct number of ai/ConvertClock pulses.
Similarly, the device ignores all ai/ConvertClock pulses until it recognizes
an ai/SampleClock pulse. Once the device receives the correct number of
ai/ConvertClock pulses, it ignores subsequent ai/ConvertClock pulses until
it receives another ai/SampleClock. Figures 4-10, 4-11, 4-12, and 4-13
show timing sequences for a four-channel acquisition (using AI channels 0,
1, 2, and 3) and demonstrate proper and improper sequencing of
ai/SampleClock and ai/ConvertClock.
ai/ConvertClockTimebase
ai/SampleClock
ai/ConvertClock
Delay
From
Sample
Clock
Convert
Period