National Instruments Deterministic Ethernet Expansion Chassis NI 9144 - Manual (Page 56)

NI 9144 User Guide and Specifications 56 ni.com
Where:
6:4 Excitation
3:0 Offset Cal Enable <ch3..ch0>
Shunt Cal Enable <3..0>
Controls the shunt calibration switch for each of the four channels. A logic 1 in any bit closes the
switch for the respective channel, while a logic 0 opens the switch.
Half Bridge Enable <3..0>
Controls the half bridge completion option for each channel. Enabling half bridge completion for a
channel disconnects the negative signal input pin from the rest of the circuit, and uses an internal
voltage equal to the midpoint of the excitation voltage as the negative input to the rest of the circuit.
A logic 1 in any bit enables half bridge completion for the respective channel, while a logic 0
disables it.
Excitation
Sets the excitation voltage setting. All channels share the same excitation voltage.
0b000 = 0 2.5 V The OCLK pin is used as the
oversample clock source.
0b001 = 1 3.3 V The 12.8 MHz internal clock is
used as the clock source and
this 12.8 MHz is driven onto
the
OCLK pin.
0b010 = 2 5.0 V The internal clock is used but
not driven onto
OCLK pin.
Currently, this is the required
clock setting.
0b011 = 3 10.0 V Reserved.
0b1xx = 4..7 External Excitation —
Table 51. NI 9237 Scan List Format (Continued)
Bits Field