National Instruments Network Device DAQ S - Manual (Page 127)

Chapter 9 Digital Routing and Clock Generation
© National Instruments Corporation 9-7 NI 6124/6154 User Manual
The following is an example of low to high transitions of the input signal.
High to low transitions work similarly.
Assume that an input terminal has been low for a long time. The input
terminal then changes from low to high, but glitches several times. When
the filter clock has sampled the signal high on N consecutive edges, the low
to high transition is propagated to the rest of the circuit. The value of N
depends on the filter setting; refer to Table 9-2.
The filter setting for each input can be configured independently. On power
up, the filters are disabled. Figure 9-3 shows an example of a low to high
transition on an input that has its filter set to 125 ns (N = 5).
Figure 9-3. Filter Example
Enabling filters introduces jitter on the input signal. For the 125 ns and
6.425
μs filter settings, the jitter is up to 25 ns. On the 2.56 ms setting,
the jitter is up to 10.025
μs.
When a PFI input is routed directly to RTSI, or a RTSI input is routed
directly to PFI, the S Series device does not use the filtered version of
the input signal.
Table 9-2. Filters
Filter Setting
N (Filter Clocks
Needed to
Pass Signal)
Pulse Width
Guaranteed to
Pass Filter
Pulse Width
Guaranteed to
Not Pass Filter
125 ns 5 125 ns 100 ns
6.425
μs
257 6.425
μs
6.400
μs
2.56 ms ~101,800 2.56 ms 2.54 ms
Disabled — — —
1 2 3 1 4 1 2 3 4 5
RTSI, PFI, or
PXI_STAR Terminal
Filter Clock
(40 MHz)
Filtered Input
Filtered input goes
high when terminal
is sampled high on
five consecutive filter
clocks.