Figure 7-25. continuous pulse train generation, Finite pulse train generation, Figure 7-26. finite pulse train timing diagram – National Instruments Network Device DAQ S User Manual

Page 94: Finite pulse train generation -22

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Chapter 7

Counters

NI 6124/6154 User Manual

7-22

ni.com

You also can use the Gate input of the counter as a Pause Trigger (if it is not
used as a Start Trigger). The counter pauses pulse generation when the
Pause Trigger is active.

Figure 7-25 shows a continuous pulse train generation (using the rising
edge of Source).

Figure 7-25. Continuous Pulse Train Generation

Continuous pulse train generation is sometimes called frequency division.
If the high and low pulse widths of the output signal are M and N periods,
then the frequency of the Counter n Internal Output signal is equal to the
frequency of the Source input divided by M + N.

For information about connecting counter signals, refer to the

Default

Counter/Timer Pinouts

section.

Finite Pulse Train Generation

This function generates a train of pulses of predetermined duration. This
counter operation requires both counters. The first counter (for this
example, Counter 0) generates a pulse of desired width. The second
counter, Counter 1, generates the pulse train, which is gated by the pulse of
the first counter. The routing is done internally. Figure 7-26 shows an
example finite pulse train timing diagram.

Figure 7-26. Finite Pulse Train Timing Diagram

SOURCE

OUT

Counter Armed

Counter 0

(Paired Counter)

Counter 1

Generation

Complete

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