Document Outline

• List of Figures
• List of Tables
• Overview
  • Physical Media Attachment (PMA)
  • Clocking
  • Physical Coding Sublayer (PCS)
  • Debug and Test
  • Major standards supported
  • SerDes Placement
  • SerDes Architecture Overview
• Physical Media Attachment (PMA)
  • 1. Common
  • 2. Receiver (RX)/Transmitter (TX)
  • 3. Digital PMA (DPMA)
• PCS Blocks in the Transmitter (TX)
  • PCS Self Test Logic
  • Polarity bit reversal (PBR) #0 and #1
    • Polarity and Bit Inversion – 10/20 bit Operation
    • Polarity and Bit Inversion – 8/16 bit Operation
  • Interface Encapsulation
  • 8b/10b Encoder
    • Symbols and Comma Character
  • Running Disparity
• PCS Blocks in the Receiver (RX)
  • Transition Density Checker (TDC)
  • Polarity Bit Reversal (PBR)
  • Symbol Alignment
    • Modes of Operation
      • Manual Mode:
      • Bit Slip Mode:
      • Automatic Mode:
  • Deskew FIFO
    • Functional Description
  • Lane-to-Lane Deskew Modes of Operation
    • The deskew module can work in three modes:
      • Manual Mode:
      • Auto Mode:
      • Symbol slip mode:
    • Standards Supported by Deskew Module
  • Elastic FIFO (Elastic Buffer)
    • EFIFO Standards and Skip Characters
    • EFIFO Operation
    • Overflow/Underflow
  • 8b/10b Decoder
  • Bit Slider
  • Interface Encapsulation
  • PCS Self Test Checker
• PCS Interface
  • Gigabit Ethernet Interface
  • XAUI
  • PIPE Interface
• Clocking
• Debug and Test
  • Loopback Modes
    • /PMA loopback modes:
    • /PCS loopback modes:
  • PMA Test Pattern Generator
  • PMA Test Pattern Checker
  • PCS Test Pattern Generator
  • PRBS Generator
  • PCS Test Pattern Checker
• Latency
  • PMA Latency
  • PCS Latency
• Configurations Supported
• Design Flow: Creating a SerDes Design
  • Generating SerDes Wrapper using ACE GUI
  • Single-Lane Serdes Wrapper
    • /Overview Section:
    • Section on PMA Settings:
    • RX PMA Equalization
    • RX PMA PLL
    • TX PMA Driver
    • TX PMA PLL
    • Section on PCS Settings:
    • RX PCS Settings
    • RX PCS Symbol Alignment
    • TX PCS Settings
    • Section on Manually Overriding PMA/PCS Register Values:
    • Generation of Wrapper Files:
  • Files Generated by ACE-GUI
  • Integration of SerDes Wrapper in a Design
    • Design and Wrapper Files
    • Dynamically Changing the SerDes Register Values
    • Using sBus module to enable internal loopback
  • Placement of SerDes
    • Timing Constraints
    • Test bench Setup for Simulation
  • Design Guidelines
    • Reset Sequence
    • SerDes Placement and Clocking Limitations
    • Wide Bus
    • Design Tips
  • Variants of the Simple Design
    • Design Bypassing PCS:
      • Modification – 1 (ACE GUI):
    • Bypassing PCS by Manually Overriding Corresponding Register
• Dynamic Read/Write of SerDes Registers via SBUS
  • Overview
    • Alternatives for using SBUS interface for SerDes register access:
  • ACX_SERDES_SBUS_IF Module
    • The Ports of ACX_SERDES_SBUS_IF Module:
      • General signals:
      • SerDes signals:
      • Parallel Interface signals:
      • Example of SerDes Register Access through SBUS: Setting Loopback Mode
      • SerDes signals
      • Control signals
      • Pass-through signals:
    • Loopback Modes
• SerDes Registers
• Electrical Specifications
  • Operating Conditions
  • Transmitter
  • Receiver
    • Eye Diagram
  • Reference Clock
    • Jitter Specification
• Revision History