ADLINK cPCI-9116 - Manual (Page 41)

Registers
• 31
TimeBase(bit5) : The Timebase Selection of 9116 series
1: External Timebase
0: Internal Timebase (24 MHz)
TrgP (bit4): The Trigger polarity selection bit
1: Negative Edge Trigger
0: Positive Edge Trigger
MODE2 ~ 0(bit3 ~ bit1): Trigger Mode Selection Bits
MODE2 MODE1 MODE0 Description
0 0 0 Software Trigger
0 0 1 Post Trigger
0 1 0 Delay Trigger
0 1 1 Pre Trigger
1 0 0 Middle Trigger
Table 15. Trigger Mode Selection Bits
4.11 Interrupt Control Register
Address: BASE + 0x38
Attribute: write
Data Format:
Bit 7 6 5 4 3 2 1 0
--- --- --- Clr_Timer Clr_STTC Clr_Hfull Clr_DTrg Clr_EOC
Bit 15 14 13 12 11 10 9 8
--- --- --- Timer_en STTC_en Hfull_en DTrg_en EOC_en
Bit 23 22 21 20 19 18 17 16
--- --- --- --- --- --- --- ---
Bit 31 30 29 28 27 26 25 24
--- --- --- --- --- --- --- ---
Table 16. Interrupt Control Register
Timer_en (bit12): General Purpose Timer Interrupt Enable Control
1: Enable
0: Disable