ADLINK cPCI-9116 - Manual (Page 58)

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• Operation Theory
DMA Transfer
PCI bus-mastering DMA is necessary for high speed DAQ in order to utilize the
maximum PCI bandwidth. The bus-mastering controller, which is built-in into
the AMCC-5933 PCI controller, controls the PCI bus when it becomes the
master on the bus. Bus mastering reduces the size of the on-board memory
and reduces the CPU loading because data is directly transferred to the
computer’s memory without host CPU intervention.
Bus-mastering DMA provides the fastest data transfer rates on PCI-bus. Once
the analog input operation starts, control returns to your program. The
hardware temporarily stores the acquired data in the onboard Data FIFO and
then transfers the data to a user-defined DMA buffer memory in the computer.
Note that even when the acquired data length is less than the Data FIFO, the
AD data will not held in the Data FIFO but directly transferred to the host
memory by bus-mastering DMA.
The DMA transfer mode is very complex to program. We recommend using a
high-level program library to configure this card. If you want to program the
software, which can handle DMA bus master data transfer, please refer to
information about the PCI controller at www.amcc.com.
Note: In DMA transfer mode, the maximum acquired data length in one
acquisition can be up to 64M bytes (32M samples), which is the limit of the
PCI controller. However, the memory that you allocate for data transfer
must be continuous.
5.2 Digital Input and Output
To program the digital I/O operation is fairly straightforward. The digital input
(DI) operation is to read data from its corresponding registers, and the digital
output (DO) operation is to write data to its corresponding registers. The digital
I/O registers‘ formats are shown in section 4.9. The DO can be read back when
reading the DI port. Note that the DIO data channel can only be read or written
to, in the form of 16-bit blocks. It is impossible to access individual bits.