Altera DisplayPort MegaCore Function - Manual (Page 15)

• Simulate the behavior of a licensed IP core in your system.
• Verify the functionality, size, and speed of the IP core quickly and easily.
• Generate time-limited device programming files for designs that include IP cores.
• Program a device with your IP core and verify your design in hardware.
OpenCore Plus evaluation supports the following two operation modes:
• Untethered—run the design containing the licensed IP for a limited time.
• Tethered—run the design containing the licensed IP for a longer time or indefinitely. This requires a
connection between your board and the host computer.
Note: All IP cores that use OpenCore Plus time out simultaneously when any IP core in the design times
out.
Specifying IP Core Parameters and Options
Follow these steps to specify the DisplayPort IP core parameters and options.
1. Create a Quartus II project using the New Project Wizard available from the File menu.
2. On the Tools menu, click IP Catalog.
3. Under Installed IP, double-click Library > Interface > Protocols > Audio&Video > DisplayPort.
The parameter editor appears.
4. Specify a top-level name for your custom IP variation. This name identifies the IP core variation files
in your project. If prompted, also specify the targeted Altera device family and output file HDL
preference. Click OK.
5. Specify parameters and options in the DisplayPort parameter editor:
• Optionally select preset parameter values. Presets specify all initial parameter values for specific
applications (where provided).
• Specify parameters defining the IP core functionality, port configurations, and device-specific
features.
• Specify options for generation of a timing netlist, simulation model, testbench, or example design
(where applicable).
• Specify options for processing the IP core files in other EDA tools.
6. Click Generate to generate the IP core and supporting files, including simulation models.
7. Click Close when file generation completes.
8. Click Finish.
9. If you generate the DisplayPort IP core instance in a Quartus II project, you are prompted to add
Quartus II IP File (.qip) and Quartus II Simulation IP File (.sip) to the current Quartus II project.
Simulating the Design
You can simulate your DisplayPort IP core variation using the simulation model that the Quartus II
software generates. The simulation model files are generated in vendor-specific subdirectories of your
project directory. The DisplayPort IP core includes a simulation example.
The following sections teach you how to simulate the generated DisplayPort IP core variation with the
generated simulation model.
3-2 Specifying IP Core Parameters and Options
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2015.05.04
Altera Corporation Getting Started
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