Altera DisplayPort MegaCore Function - Manual (Page 61)

Figure 5-11: Sink Clock Tree
Audio
Decoder
Back-End
Video FIFO
AUX
Controller
Controller
Interface
DCFIFO
Front-End
Decoder
DCFIFO
DCFIFO
DCFIFO
HSSIO0
HSSIO1
HSSIO2
HSSIO3
rx_ss_clk
clk
rxN_vid_clk
aux_clk
Legend
Recovered Clock
from Transceiver
(rx_ss_clk)
Audio Data
Pixel Clock
(rxN_vid_clk)
Secondary
Stream Data
Video Data
clk
aux_clk
DisplayPort Decoder Transceiver Block
270/135/81/67.5/40.5 MHz
Main
Link 0
Main
Link 1
Main
Link 2
Main
Link 3
135 MHz Transceiver Reference Clock Signals from PLL or Dedicated Pin
Related Information
Clock Recovery Core on page 6-4
Provides more information about determining the optimum frequency.
UG-01131
2015.05.04
Sink Clock Tree 5-25
DisplayPort Sink Altera Corporation
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