Altera DisplayPort MegaCore Function - Manual (Page 157)

Bit Bit Name Function
23
Unused
22:21
PHY_SINK_TEST_LANE_
SEL
Specifies the lane that is being tested, when
PHY_SINK_
TEST_LANE_EN
is 1,
• 00 = Lane 0
• 01 = Lane 1
• 10 = Lane 2
• 11 = Lane 3
20
PHY_SINK_TEST_LANE_
EN
Writing this bit at 1 enables single lane PHY test, Write 0
to disable single lane PHY test.
19 RST3 Writing this bit at 1 resets the lane 3 bit-error counter in
register
DPRX_BER_CNT1
. Always reads as 0.
18 RST2 Writing this bit at 1 resets the lane 2 bit-error counter in
register
DPRX_BER_CNT1
. Always reads as 0.
17 RST1 Writing this bit at 1 resets lane 1 bit-error counter in
register
DPRX_BER_CNT0
. Always reads as 0.
16 RST0 Writing this bit at 1 resets lane 0 bit-error counter in
register
DPRX_BER_CNT0
. Always reads as 0.
15:14 Unused
13:11 PATT3 Pattern selection for lane 3:
• 000 = No test pattern (normal mode)
• 011 = PRBS7
• 101 = HBR2Compliance EYE pattern
10:8 PATT2 Pattern selection for lane 2:
• 000 = No test pattern (normal mode)
• 011 = PRBS7
• 101 = HBR2 Compliance EYE pattern
7:5 PATT1 Pattern selection for lane 1:
• 000 = No test pattern (normal mode)
• 011 = PRBS7
• 101 = HBR2 Compliance EYE pattern
4:2 PATT0 Pattern selection for lane 0:
• 000 = No test pattern (normal mode)
• 011 = PRBS7
• 101 = HBR2 Compliance EYE pattern
10-6 DPRX_BER_CONTROL
UG-01131
2015.05.04
Altera Corporation DisplayPort Sink Register Map and DPCD Locations
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