Altera DisplayPort MegaCore Function User Manual
Page 43
Interface
Port Type
Clock Domain
Port
Direction
Description
rx_mgmt AV-MM
clk
rx_mgmt_address[8:0]
Input
Avalon-MM interface
for embedded
controller
rx_mgmt_chipselect
Input
rx_mgmt_read
Input
rx_mgmt_write
Input
rx_mgmt_
writedata[31:0]
Input
rx_mgmt_readdata[31:0]
Outp
ut
rx_mgmt_waitrequest
Outp
ut
rx_mgmt_
irq
IRQ
clk
rx_mgmt_irq
Output
Interrupt for
embedded controller
Table 5-3: Transceiver Management Interface
Interface
Port Type
Clock Domain
Port
Direction
Description
xcvr_
mgmt_clk
Clock
N/A
xcvr_mgmt_clk
Input
Transceiver
management clock
clk_cal
Clock
N/A
clk_cal
Input
Calibration clock
rx_
reconfig
Conduit
xcvr_mgmt_
clk
rx_link_rate[1:0]
Output
Transceiver link rate
reconfiguration
handshaking
rx_link_rate_
8bits[7:0]
Outp
ut
rx_reconfig_req
Outp
ut
rx_reconfig_ack
Input
rx_reconfig_busy
Input
Note: Value of rx_link_rate[1:0]: 0=1.62Gbps, 1=2.70Gbps, 2=5.40Gbps; value of rx_link_rate_8bits[7:0]:
0×06=1.62Gbps, 0×0a=2.70Gbps, 0×14=5.40Gbps
UG-01131
2015.05.04
Sink Interfaces
5-7
DisplayPort Sink
Altera Corporation