Altera DisplayPort MegaCore Function - Manual (Page 193)

Date Version Changes
• Changed the value of the following source register bits:
• 0×0000 - Bits
RX_LINK_RATE
• 0×0001 - Bits
RX_LINK_RATE
• 0×0002 - Bits
RSTI3, RSTI2, RSTI1, RSTI0
• Added new signals:
clk_cal
Calibration clock for transceiver
management interface
tx_link_rate_
8bits
rx_link_rate_
8bits
Main link rate expressed in multiples of
270Mbps —
txN_video_in
txN_vid_clk
txN_audio
txN_audio_clk
txN_ss
txN_msa_
conduit
TX signals for Stream 1, 2, and 3
rxN_video_out
rxN_vid_clk
rxN_audio
rxN_ss
rxN_msa_
conduit
rxN_stream
RX signals for Stream 1, 2, and 3
• Changed the following signal names:
•
rx_xcvr_clkout
to
rx_ss_clk
•
tx_xcvr_clkout
to
tx_ss_clk
UG-01131
2015.05.04
Document Revision History A-3
Additional Information Altera Corporation
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