A. additional information, Document revision history, Additional information – Altera DisplayPort MegaCore Function User Manual
Page 191
Additional Information
A
2015.05.04
UG-01131
Document Revision History
The following table lists the revision history for this document.
Table A-1: Document Revision History
Date
Version
Changes
May 2015
2015.05.04
• Added Arria 10 support.
• Updated color support:
• RGB—18, 24, 30, 36, or 48 bpp
• YCbCr 4:4:4—24, 30, 36, or 48 bpp
• YCbCr 4:2:2—16, 20, 24, or 32 bpp
• Removed information about Link Quality Generation register.
These bits are now combined into the
DPTX_TX_CONTROL
register.
• Added information about
DPTX_TEST_80BIT_PATTERN1-3
bits.
• Added source-supported DPCD locations.
• Added new sink-supported DPCD location bits:
TEST_REQUEST
,
TEST_LINK_RATE
,
TEST_LANE_COUNT
,
PHY_TEST_PATTERN
, and
TEST_80BIT_CUSTOM_PATTERN
.
• Added Arria 10 information for the DisplayPort IP core hardware
demonstration and simulation example.
December 2014 2014.12.30
Edited the DisplayPort RX link rate (Clock Recovery interface) for
HBR2 from 4.50 Gbps to 5.40 Gbps.
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