Altera HyperTransport MegaCore Function - Manual (Page 17)

Chapter 2: Getting Started 2–9
MegaCore Function Walkthrough
© November 2009 Altera Corporation HyperTransport MegaCore Function User Guide
9. Click Finish. The Parameterize—HyperTransport MegaCore Function
Parameterize panel closes and you are returned to the IP Toolbench interface.
Step 2: Set Up Simulation
An IP functional simulation model is a cycle-accurate VHDL or Verilog HDL model
file produced by the Quartus II software. The simulation model allows for fast
functional simulation of IP using industry-standard VHDL and Verilog HDL
simulators.
1
You may only use these simulation model output files for simulation purposes and
expressly not for synthesis or any other purposes. Using these models for synthesis
creates a nonfunctional design.
To generate an IP functional simulation model for your MegaCore function, follow
these steps:
1. In the IP Toolbench, click Step 2: Set Up Simulation, as shown in Figure 2–9 .
Figure 2–8. Parameterize—Advanced Settings Tab