Altera HyperTransport MegaCore Function - Manual (Page 46)

3–20 Chapter 3: Specifications
HyperTransport MegaCore Function Specification
HyperTransport MegaCore Function User Guide © November 2009 Altera Corporation
Preliminary
Rx Command/Data Buffer Timing Diagrams
Figure 3–10 shows a 32-byte (8 double-word) packet received across the Rx response
buffer interface. In this example, the user-side logic asserts Ena_i in response to
Dav_o . The Rx posted and Rx non-posted buffers behave in the same manner, except
that posted and non-posted commands are typically 8 bytes. Thus, Dat_o[63:32]
would be valid as well as Sop_o .
Figure 3–11 is similar to Figure 3–10 except that Ena_i is always asserted so that the
data transfer begins the clock cycle after Dav_o is asserted. Additionally, the example
in Figure 3–11 is only 28 bytes long to show the behavior of Mty[2:0] during Eop_o .
Figure 3–10. Single 32-Byte Read Response across Rx Interface, No Wait States Timing Diagram
Notes to Figure 3–10 :
(1) Dav_o is shown to deassert, indicating that the Rx buffer does not have any additional packets stored beyond the one that is currently being read.
(2) Ena_i is a Don’t Care during this time because Dav_o is not asserted.
(3) Dat_o[63:32] is not valid during this time because the command is only a 4-byte read response.
2 3 4 5 6 7 9 10
RefClk
Dav_o
8 1
Ena_i
Dat_o[31:0]
Dat_o[63:32]
Val_o
Sop_o
Eop_o
Mty_o[2:0]
11
RdResp DW0 DW2 DW4 DW6
DW1 DW3 DW5 DW7
0b000
(3)
(2)
(1)
Figure 3–11. 28-Byte Read Response across Rx Interface, No Wait States, Ena_i Asserted Timing Diagram
Notes to Figure 3–11 :
(1) Ena_i is a Don’t Care during this time because Dav_o is not asserted
(2) Dat_o[63:32] is not valid during this time because the command is only a 4-byte read response.
(3) Dat_o[63:32] is not valid during this time because the response is only seven double-words long.
2 3 4 5 6 7 9 10
RefClk
Dav_o
8 1
Ena_i
Dat_o[31:0]
Dat_o[63:32]
Val_o
Sop_o
Eop_o
Mty_o[2:0]
11
RdResp DW0 DW2 DW4 DW6
DW1 DW3 DW5 (2)
(1)
(3)
0b000 0b100