Altera HyperTransport MegaCore Function - Manual (Page 21)

Chapter 2: Getting Started 2–13
Simulate the Design
© November 2009 Altera Corporation HyperTransport MegaCore Function User Guide
Simulate the Design
To simulate your design, you use the IP functional simulation models generated by
the IP Toolbench. The IP Functional Simulation model is the .vo or .vho file generated
by the IP Toolbench, as specified in
“Step 2: Set Up Simulation” on page 2–9 . Add this
file in your simulation environment to perform functional simulation of your custom
variation of the MegaCore function.
The HyperTransport MegaCore function vector-based testbench is an example you
can use to help set up your own simulation environment. You should not attempt to
edit these files. For information about how to perform a simulation using this
vector-based testbench, see
“Example Simulation and Compilation” on page 2–16 .
f For more information about IP functional simulation models, refer to the Simulating
Altera IP in Third-Party Simulation Tools chapter in volume 3 of the Quartus II Handbook.
You can use any Altera-supported third-party simulator to simulate your design and
testbench.
Compile the Design
You can use the Quartus II software to compile your design. Refer to Quartus II Help
for instructions on compiling your design.
The instructions in this section assume that you named your wrapper file
ht_example.v
using the MegaWizard Plug-In Manager. If you chose a different name,
substitute that name when following the instructions.
To compile your design in the Quartus II software, perform the following steps:
1. If you are using the Quartus II software to synthesize your design, skip to step 2 . If
you are using a third-party synthesis tool to synthesize your design, perform the
following steps:
a. Set a black box attribute for ht_example.v before you synthesize the design.
Refer to the Quartus II Help for your specific synthesis tool for instructions on
setting black-box attributes.
b. Run the synthesis tool to produce an EDIF Netlist File (.edf) or Verilog Quartus
Mapping file (.vqm) for input to the Quartus II software.
c. Add the .edf or .vqm file to your Quartus II project.
2. On the Processing menu, point to Start and click Start Analysis & Elaboration to
elaborate the design.
3. On the Assignments menu, click Assignment Editor.
4. If the pin names are not displayed, on the View menu, click Show All Known Pin
Names .