Altera HyperTransport MegaCore Function - Manual (Page 6)

1–2 Chapter 1: About this MegaCore Function
Introduction
HyperTransport MegaCore Function User Guide © November 2009 Altera Corporation
Preliminary
Introduction
The HyperTransport MegaCore function implements high-speed packet transfers
between physical (PHY) and link-layer devices, and is fully compliant with the
HyperTransport I/O Link Specification, Revision 1.03. This MegaCore function allows
designers to interface to a wide range of HyperTransport™ technology (HT) enabled
devices quickly and easily, including network processors, coprocessors, video
chipsets, and ASICs.
Features
The HyperTransport MegaCore function has the following features:
■ 8-bit fully integrated HT end-chain interface
■ Packet-based protocol
■ Dual unidirectional point-to-point links
■ Up to 16 Gigabits per second (Gbps) throughput (8 Gbps in each direction)
■ 200, 300, and 400 MHz DDR links in Stratix and Stratix GX devices
■ 200, 300, 400, and 500 MHz DDR links in Stratix II and Stratix II GX devices
■ Low-swing differential signaling with 100- differential impedance
■ Hardware verified with HyperTransport interfaces on multiple industry standard
processor and bridge devices
■ Fully parameterized MegaCore function allows flexible, easy configuration
■ Fully optimized for the Altera Stratix II, Stratix, Stratix GX, and Stratix II GX
device families
■ Application-side interface uses the Altera Atlantic TM interface standard
■ Manages HT flow control, optimizing performance and ease of use
■ Independent buffering for each HT virtual channel
■ Automatic handling of HT ordering rules
■ Stalling of one virtual channel does not delay other virtual channels (subject to
ordering rules)
■ Flexible parameterized buffer sizes, allowing customization depending on
system requirements
■ User interface has independent interfaces for the HT virtual channels, allowing
independent user logic design
■ Cyclic redundancy code (CRC) generation and checking to preserve data integrity
■ Integrated detection and response to common HT error conditions
■ CRC errors
■ End-chain errors
■ Fully integrated HT configuration space includes all required configuration space
registers and HT capabilities list registers