Altera HyperTransport MegaCore Function - Manual (Page 49)

Chapter 3: Specifications 3–23
HyperTransport MegaCore Function Specification
© November 2009 Altera Corporation HyperTransport MegaCore Function User Guide
Preliminary
Table 3–7. Tx Command/Data Buffer Interface Signals (Part 1 of 2)
Signal Name Direction Description
Dat_i[63:0] Input Data bus. This 64-bit input bus carries the data input to the command/data buffer. Data is
loaded in little endian format (least significant byte is loaded first on
Dat_i[7:0] ).
Mty_i[2:0] Input Data byte empty. This bus indicates which bytes are invalid on Dat_i[63:0] . Because
HT packets are DWORD aligned, there are only two valid encodings used by the
HyperTransport MegaCore function. The following
Mty_i signal values are acceptable:
Mty_i = ‘000’ , all bytes on Dat_i[63:0] are valid.
Mty_i = ‘100’ , Dat_i[63:32] are invalid.
Invalid bytes can only be on the last word of a packet. It is illegal to have a non-zero value
for the
Mty_i signals for words other than the last word of the packet, even for 32-bit
commands that have data, such as a read response. In this case, when Sop_i is asserted,
Dat_i[63:32] is implicitly invalid. The first data bytes are placed on the Dat_i bus
the cycle after the Sop_i .
If the 32-bit command does not have data, the Mty_i signals should be set to ‘100’ and
Eop_i and Sop_i should be asserted.
Sop_i Input Start of packet. This signal must be high at the start of the packet. Start of packet is always
loaded with least significant bytes loaded first. The first 64-bit word of a packet must
always be the command. If the command is only 32 bits, it must be loaded on
Dat[31:0] and the buffer ignores Dat_i[63:32] .
Eop_i Input End of packet. This signal indicates the end of packet. Eop_i must be high at the end of
the packet. When this signal is high, the Mty_i signals can indicate that Dat_i[63:32]
are invalid.
WrRjct_o Output Write reject. This signal indicates that the local-side application’s attempted write into the
buffer has been rejected due to an error. The following errors cause the
WrRjct_o signal
to be asserted:
■ A write is attempted while Dav_o is low.
■ A write of the first word of a packet (command) was performed without Sop_i
asserted.
■ A write is attempted that has more than 9 valid cycles. The maximum transfer is the HT
command packet followed by a 64 byte HT data packet.
If any of the above errors are detected, the write is rejected; the internal address counters
and buffer status registers are reset to indicate that there were no writes after the last
successful packet. Packets that were written into the buffer before the packet with the error
are not affected and are transmitted to the link as usual.
The WrRjct_o signal is intended for use as a debugging signal for simulation and early
prototypes.