Altera HyperTransport MegaCore Function - Manual (Page 24)

2–16 Chapter 2: Getting Started
Example Simulation and Compilation
HyperTransport MegaCore Function User Guide © November 2009 Altera Corporation
1 Altera recommends that you give the file a unique name, for example,
<MegaCore name>_license.dat.
1. Run the Quartus II software.
2. On the Tools menu, click License Setup. The Options dialog box opens to the
License Setup page.
3. In the License file box, add a semicolon to the end of the existing license path and
file name.
4. Type the path and file name of the MegaCore function license file after the
semicolon.
1 Do not include any spaces either around the semicolon or in the path or file
name.
5. Click OK to save your changes.
Example Simulation and Compilation
Altera provides example design files in the directory <path>\ht\example, where
<path> is the directory in which you installed the MegaCore function. You can use
these design files to run vector-based simulations and to compile in the Quartus II
software. The example can help you validate the installation of the HyperTransport
MegaCore function in your design environment and serve as an example for setting
up your custom environment.
Example Quartus II Project
Altera provides an example Quartus II project in the directory
<path>\ht\example\quartus that compiles the file <path>\ht\example\ht_top.v.
This project has Quartus II virtual pins assigned for the user-side signals from the
MegaCore function variation. The target device is the EP1S60F1020C6. The pin
assignments used for the HyperTransport link signals support all clocking options.
To compile this example Quartus II project, perform the following steps in the
Quartus II software version 9.1:
1. Start the Quartus II software.
2. On the File menu, click Open Project.
3. In the Open Project dialog box, browse to <path>\ ht\example\quartus.
4. Select the ht_top.qpf file.
5. On the Processing menu, click Start Compilation to compile the project.
Example Simulation with Test Vectors
The example design in directory <path>\ht\example contains the following Verilog
HDL files used in the example simulation:
■ ht_top.vo
■ ht_top_tb.v