Altera HyperTransport MegaCore Function - Manual (Page 32)

3–6 Chapter 3: Specifications
HyperTransport MegaCore Function Specification
HyperTransport MegaCore Function User Guide © November 2009 Altera Corporation
Preliminary
If the Rx request address matches one of the BAR registers in the CSR module, the Rx
packet processor claims the packet and writes to the Rx posted buffer or the Rx
non-posted buffer. If the UnitID in an Rx response matches the UnitID in the CSR, the
processor claims the packet and writes to the Rx response buffer. The processor claims
data packets and writes to the appropriate Rx buffer if it claimed the associated
request or response packet.
The Rx packet processor passes unclaimed packets to the end-chain handler.
End-Chain Handler
The end-chain handler logs errors when it receives a response or posted packet. It also
generates NXA response packets when it receives a non-posted packet.
Rx Claimed Buffers
The traffic written to the claimed packet buffers is stored in the appropriate virtual
channel buffer. The packets are stored in the order in which they are received from the
link. When reading the packets from the buffers, you read commands followed by any
associated data.
To allow maximum throughput of the command packets, command packets are
stored in registers. Data packets, on the other hand, are stored in dual-port memory
blocks.
Although data packets and command packets are stored in separate storage elements,
when the user interface reads those packets it appears as though they are stored in the
same location. That is, the user interface sees a command packet followed by the data,
consecutively.
Tx Buffers
The Tx buffers are temporary storage for the traffic to be transmitted on the Tx path.
The user logic writes packets to the buffer with the command as the first word written
followed by any data associated with that command. Tx buffers automatically adjust
for 32-bit commands or 64-bit commands by inserting idle NOP packets in the upper
bits of a 32-bit command, such as a read response. Additionally, because the
transmitted data may be an odd number of DWORDS, the Tx buffers insert a
NOP
packet from the NOP generator to align the end of packet to the 64-bit boundary,
placing the next packet start command on the lower DWORD. The Tx buffers also
generate appropriate CTL information for transmission to the link.
Scheduler
The scheduler ensures equal access to all HT virtual channels. The scheduler is an
arbiter that performs round-robin arbitration between the response, non-posted, and
posted buffers. Additionally, the scheduler gives a higher priority to the NOP
generator so that if a NOP packet with flow control information is available at the end
of a packet transmission, the scheduler allows it to be transmitted before starting a
new packet transmission from another virtual channel.