Altera HyperTransport MegaCore Function - Manual (Page 31)

Chapter 3: Specifications 3–5
HyperTransport MegaCore Function Specification
© November 2009 Altera Corporation HyperTransport MegaCore Function User Guide
Preliminary
Rx Synchronization and Alignment Interface
The Rx synchronization and alignment interface performs the following functions:
■ Bit-to-Byte Alignment—The interface performs link initialization sync packet
detection and byte alignment so that the first received byte of data is placed in byte
0 of the internal 64-bit data path.
■ CRC Checking—The interface checks the link CRC.
■ Synchronization—The interface writes all non-CRC data to an Rx synchronization
FIFO buffer so that the data can be synchronized to the protocol interface clock
domain for the protocol interface layer.
1 If you turn on the Shared Rx/Tx/Ref Clock option in the IP Toolbench
parameterization wizard, the IP Toolbench removes the Rx synchronization
FIFO buffer from the design to reduce latency. Refer to
“Clocking Options”
on page 3–7 for more information about clock options.
Tx Alignment Interface
The Tx alignment interface performs the following functions:
■ Synchronization—The interface reads transmit data from the Tx synchronization
FIFO buffer to move the data from the protocol interface clock domain to the Tx
alignment clock domain.
1 If you turn on the Shared Ref/Tx Clock or Shared Rx/Tx/Ref Clock option
in the wizard, the wizard removes the Tx synchronization FIFO buffer from
the design to reduce latency. Refer to
“Clocking Options” on page 3–7 for
more information about clock options.
■ Link Initialization—The interface generates the link initialization sequence when
the link is reset.
■ CRC Generation—The interface generates CRCs.
Protocol Interface
The protocol interface module has a 64-bit data path. It receives formatted packets
from the Rx synchronization and alignment module and transmits packets to the Tx
alignment module. Because the HT specification requires that traffic in the three
different virtual channels (posted, non-posted, and responses) be kept independent,
the module maintains internal packet buffering and the local interface separately for
each virtual channel. The following sections describe the protocol interface blocks and
their function.
Rx Packet Processor
The Rx packet processor reads the data stream from the Rx sync FIFO buffer. It parses
the data and determines whether packets should be claimed or passed to the end
chain handler.