Altera Stratix IV GX FPGA Development Board - Manual (Page 22)

2–14 Chapter 2: Board Components
Configuration, Status, and Setup Elements
Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation
Each jumper shown in Figure 2–4 is located in the JTAG DIP switch (SW6) on the back
of the board. To connect a device or interface in the chain, their corresponding switch
must be in the down position. Push all the switches in the up position to only have the
FPGA in the chain.
The MAX II CPLD EPM2210 System Controller must be in the chain to use some of the
GUI interfaces. For this setting, push the left-most switch in the down position and all
other switches in the up position.
Flash Programming
Flash programming is possible through a variety of methods using the Stratix IV GX
device.
The default method is to use the factory design called the Board Update Portal. This
design is an embedded webserver, which serves the Board Update Portal web page.
The web page allows you to select new FPGA designs including hardware, software,
or both in an industry-standard S-Record File (.flash) and write the design to the user
hardware page (page 1) of the flash over the network.
The secondary method is to use the pre-built PFL design included in the development
kit. The development board implements the Altera PFL megafunction for flash
programming. The PFL megafunction is a block of logic that is programmed into an
Altera programmable logic device (FPGA or CPLD). The PFL functions as a utility for
writing to a compatible flash device. This pre-built design contains the PFL
megafunction that allows you to write either page 0, page 1, or other areas of flash
over the USB interface using the Quartus II software. This method is used to restore
the development board to its factory default settings.
Other methods to program the flash can be used as well, including the Nios ® II
processor.
f
For more information on the Nios II processor, refer to the Nios II Processor page of
the Altera website.
FPGA Programming from Flash Memory
On either power-up or by pressing the reset configuration push-button switch (S1),
the MAX
II CPLD EPM2210 System Controller’s parallel flash loader (PFL) configures
the FPGA from the flash memory. The PFL megafunction reads 16-bit data from the
flash memory and converts it to fast passive parallel (FPP) format. This 8-bit data is
then written to the FPGA’s dedicated configuration pins during configuration.
Figure 2–5 shows the PFL configuration.