Altera Stratix IV GX FPGA Development Board - Manual (Page 70)

2–62 Chapter 2: Board Components
Memory
Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation
U32.D7 Address bus FSM_A16
2.5-V
AP35
U32.C5 Address bus FSM_A15 AL32
U32.B5 Address bus FSM_A14 AK32
U32.A5 Address bus FSM_A13 AU33
U32.C4 Address bus FSM_A12 AT33
U32.D3 Address bus FSM_A11 AH30
U32.C3 Address bus FSM_A10 AJ31
U32.B3 Address bus FSM_A9 AR34
U32.A3 Address bus FSM_A8 AT34
U32.C2 Address bus FSM_A7 AE27
U32.A2 Address bus FSM_A6 AD27
U32.D2 Address bus FSM_A5 AP34
U32.D1 Address bus FSM_A4 AN33
U32.C1 Address bus FSM_A3 AD26
U32.B1 Address bus FSM_A2 AC26
U32.A1 Address bus FSM_A1 AP33
U32.E7 Data bus FSM_D16 C33
U32.G7 Data bus FSM_D15 N31
U32.H5 Data bus FSM_D14 M31
U32.F5 Data bus FSM_D13 C32
U32.F4 Data bus FSM_D12 B32
U32.F3 Data bus FSM_D11 J32
U32.E3 Data bus FSM_D10 H32
U32.E1 Data bus FSM_D9 D35
U32.H7 Data bus FSM_D8 C35
U32.G6 Data bus FSM_D7 N28
U32.G5 Data bus FSM_D6 M28
U32.E5 Data bus FSM_D5 D31
U32.E4 Data bus FSM_D4 C31
U32.G3 Data bus FSM_D3 K30
U32.E2 Data bus FSM_D2 J30
U32.F2 Data bus FSM_D1 D34
U32.E6 Data bus FSM_D0 C34
U32.D4 Clock FLASH_CLK AF26
U32.B4 Reset FLASH_RESETn AL30
U32.F8 Chip enable FLASH_CEn AU31
U32.G8 Output enable FLASH_OEn AG27
Table 2–56. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 3)
Board Reference Description
Schematic Signal Name
I/O Standard
Stratix IV GX
Device
Pin Number