Altera Stratix IV GX FPGA Development Board - Manual (Page 63)

Chapter 2: Board Components 2–55
Memory
November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual
U22.M11 Write data bus QDR2TOP0_D2
1.5-V HSTL Class I
E25
U22.N11 Write data bus QDR2TOP0_D1 G25
U22.P10 Write data bus QDR2TOP0_D0 F25
U22.B6 Write clock P QDR2TOP0_K_P P23
U22.A6 Write clock N QDR2TOP0_K_N N23
U22.A4 Write port select QDR2TOP0_WPSn K24
U22.B7 Write byte write select 0 QDR2TOP0_BWSn0 L23
U22.A5 Write byte write select 1 QDR2TOP0_BWSn1 J25
U22.R6 Termination enable QDR2TOP0_ODT A22
U22.P3 Read data bus QDR2TOP0_Q17 M25
U22.N3 Read data bus QDR2TOP0_Q16 L25
U22.L2 Read data bus QDR2TOP0_Q15 N25
U22.K3 Read data bus QDR2TOP0_Q14 P25
U22.G3 Read data bus QDR2TOP0_Q13 G27
U22.F2 Read data bus QDR2TOP0_Q12 F27
U22.E3 Read data bus QDR2TOP0_Q11 D28
U22.D3 Read data bus QDR2TOP0_Q10 E28
U22.B2 Read data bus QDR2TOP0_Q9 D29
U22.B11 Read data bus QDR2TOP0_Q8 E29
U22.C10 Read data bus QDR2TOP0_Q7 F28
U22.E11 Read data bus QDR2TOP0_Q6 G29
U22.F11 Read data bus QDR2TOP0_Q5 J26
U22.J10 Read data bus QDR2TOP0_Q4 K26
U22.K11 Read data bus QDR2TOP0_Q3 J27
U22.L11 Read data bus QDR2TOP0_Q2 L26
U22.M10 Read data bus QDR2TOP0_Q1 K28
U22.P11 Read data bus QDR2TOP0_Q0 M27
U22.A11 Read clock P QDR2TOP0_CQ_P H28
U22.A1 Read clock N QDR2TOP0_CQ_N K27
U22.A8 Read port select QDR2TOP0_RPSn C27
U22.P6 Read data valid QDR2TOP0_QVLD H26
U22.H1 DLL enable QDR2TOP0_DOFFn B22
Table 2–50. QDRII+ Top Port 0 Pin Assignments, Signal Names and Functions (Part 2 of 2)
Board Reference Description
Schematic Signal Name
I/O Standard
Stratix IV GX
Device
Pin Number