Altera Stratix IV GX FPGA Development Board - Manual (Page 65)

Chapter 2: Board Components 2–57
Memory
November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual
U7.R8 Address bus QDR2TOP1_A1
1.5-V HSTL Class I
H19
U7.R9 Address bus QDR2TOP1_A0 C17
U7.N2 Write data bus QDR2TOP1_D17 G15
U7.M3 Write data bus QDR2TOP1_D16 F15
U7.L3 Write data bus QDR2TOP1_D15 E16
U7.J3 Write data bus QDR2TOP1_D14 D16
U7.G2 Write data bus QDR2TOP1_D13 C15
U7.F3 Write data bus QDR2TOP1_D12 C16
U7.D2 Write data bus QDR2TOP1_D11 B16
U7.C3 Write data bus QDR2TOP1_D10 A16
U7.B3 Write data bus QDR2TOP1_D9 G16
U7.C11 Write data bus QDR2TOP1_D8 G17
U7.D11 Write data bus QDR2TOP1_D7 J16
U7.E10 Write data bus QDR2TOP1_D6 K16
U7.G11 Write data bus QDR2TOP1_D5 L16
U7.J11 Write data bus QDR2TOP1_D4 P17
U7.K10 Write data bus QDR2TOP1_D3 K17
U7.M11 Write data bus QDR2TOP1_D2 N17
U7.N11 Write data bus QDR2TOP1_D1 M17
U7.P10 Write data bus QDR2TOP1_D0 P16
U7.B6 Write clock P QDR2TOP1_K_P N16
U7.A6 Write clock N QDR2TOP1_K_N M16
U7.A4 Write port select QDR2TOP1_WPSn D18
U7.B7 Write byte write select 0 QDR2TOP1_BWSn0 H17
U7.A5 Write byte write select 1 QDR2TOP1_BWSn1 J17
U7.R6 Termination enable QDR2TOP1_ODT C20
U7.P3 Read data bus QDR2TOP1_Q17 N13
U7.N3 Read data bus QDR2TOP1_Q16 N15
U7.L2 Read data bus QDR2TOP1_Q15 R14
U7.K3 Read data bus QDR2TOP1_Q14 P14
U7.G3 Read data bus QDR2TOP1_Q13 M14
U7.F2 Read data bus QDR2TOP1_Q12 N14
U7.E3 Read data bus QDR2TOP1_Q11 M13
U7.D3 Read data bus QDR2TOP1_Q10 K14
U7.B2 Read data bus QDR2TOP1_Q9 L14
U7.B11 Read data bus QDR2TOP1_Q8 E14
U7.C10 Read data bus QDR2TOP1_Q7 F14
U7.E11 Read data bus QDR2TOP1_Q6 F12
Table 2–52. QDRII+ Top Port 1 Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 3)
Board Reference Description
Schematic Signal Name
I/O Standard
Stratix IV GX
Device
Pin Number