Altera Stratix IV GX FPGA Development Board - Manual (Page 58)

2–50 Chapter 2: Board Components
Memory
Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation
U12.F2 Data bus byte lane 2 DDR3BOT_DQ18
1.5-V SSTL Class I
AN16
U12.F8 Data bus byte lane 2 DDR3BOT_DQ19 AV16
U12.H3 Data bus byte lane 2 DDR3BOT_DQ20 AP17
U12.H8 Data bus byte lane 2 DDR3BOT_DQ21 AT15
U12.G2 Data bus byte lane 2 DDR3BOT_DQ22 AR17
U12.H7 Data bus byte lane 2 DDR3BOT_DQ23 AU15
U12.E7 Write mask byte lane 2 DDR3BOT_DM2 AU16
U12.F3 Data strobe P byte lane 2 DDR3BOT_DQS_P2 AP16
U12.G3 Data strobe N byte lane 2 DDR3BOT_DQS_N2 AR16
U12.D7 Data bus byte lane 3 DDR3BOT_DQ24 AJ16
U12.C3 Data bus byte lane 3 DDR3BOT_DQ25 AM17
U12.C8 Data bus byte lane 3 DDR3BOT_DQ26 AH16
U12.C2 Data bus byte lane 3 DDR3BOT_DQ27 AL17
U12.A7 Data bus byte lane 3 DDR3BOT_DQ28 AG16
U12.A2 Data bus byte lane 3 DDR3BOT_DQ29 AH17
U12.B8 Data bus byte lane 3 DDR3BOT_DQ30 AG17
U12.A3 Data bus byte lane 3 DDR3BOT_DQ31 AK17
U12.D3 Write mask byte lane 3 DDR3BOT_DM3 AF17
U12.C7 Data strobe P byte lane 3 DDR3BOT_DQS_P3 AK16
U12.B7 Data strobe N byte lane 3 DDR3BOT_DQS_N3 AL16
U18.E3 Data bus byte lane 4 DDR3BOT_DQ32 AU23
U18.F7 Data bus byte lane 4 DDR3BOT_DQ33 AN23
U18.F2 Data bus byte lane 4 DDR3BOT_DQ34 AT23
U18.F8 Data bus byte lane 4 DDR3BOT_DQ35 AM23
U18.H3 Data bus byte lane 4 DDR3BOT_DQ36 AP23
U18.H8 Data bus byte lane 4 DDR3BOT_DQ37 AL22
U18.G2 Data bus byte lane 4 DDR3BOT_DQ38 AR23
U18.H7 Data bus byte lane 4 DDR3BOT_DQ39 AN22
U18.E7 Write mask byte lane 4 DDR3BOT_DM4 AM22
U18.F3 Data strobe P byte lane 4 DDR3BOT_DQS_P4 AT24
U18.G3 Data strobe N byte lane 4 DDR3BOT_DQS_N4 AU24
U18.D7 Data bus byte lane 5 DDR3BOT_DQ40 AR19
U18.C3 Data bus byte lane 5 DDR3BOT_DQ41 AP19
U18.C8 Data bus byte lane 5 DDR3BOT_DQ42 AP18
U18.C2 Data bus byte lane 5 DDR3BOT_DQ43 AN19
U18.A7 Data bus byte lane 5 DDR3BOT_DQ44 AT18
U18.A2 Data bus byte lane 5 DDR3BOT_DQ45 AU18
U18.B8 Data bus byte lane 5 DDR3BOT_DQ46 AW18
Table 2–46. DDR3 Bottom Port Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4)
Board Reference Description Schematic Signal
Name
I/O Standard
Stratix IV GX
Device
Pin Number