Artesyn iVPX7225 Installation and Use (April 2015) - Manual (Page 132)

FPGA Registers
iVPX7225 Installation and Use (6806800S11C) 113
7.1.18 Boot Control and Status 1 Register - 0x16
Table 7-18 Boot Control and Status 1 Register - 0x16
Bit # Description Default LPC Access I2C Access
0 Actual Boot Flash the Board is
booted from 0 RO RO
0: SPI Flash 0
1: SPI Flash 1
2:1 Last Boot Success Bits 0x0 RO RO
00: Initial value from cold reset
01: Last boot failed
10: Last boot successful
11: Don’t care
4:3 Failover Count Bits 0x0 RO RO
00: Initial value from cold reset
01: First failover
10: Second fail over
11: Don’t care
5 Reserved. 0 RO RO
6 Software Boot Flash 0 Select 0 R/W RO
0: Software has not selected flash 0
for next boot.
1: Software has selected flash 0 for
next boot.
7 Software Boot Flash 1 Select 0 R/W RO
0: Software has not selected flash 1
for next boot.
1: Software has selected flash 1 for
next boot.