Artesyn iVPX7225 Installation and Use (April 2015) - Manual (Page 162)

FPGA Registers
iVPX7225 Installation and Use (6806800S11C) 143
3 Change in data carrier detect (DDCD)
indicator
DDCD indicates that the DCD# input to the
chip has changed state since the last time it
was read by the CPU. When DDCD is set and
the modem status interrupt is enabled, a
modem status interrupt is generated. Not
supported. 0 R/W
4 Complement of the clear-to-send (CTS#)
input
When the Asynchronous Communications
Element (ACE) is in diagnostic test mode
(LOOP [MCR4] = 1), this bit is equal to the MCR
bit 1 (RTS#). Ext. R
5 Complement of the data set ready (DSR#)
input
When the ACE is in the diagnostic test mode
(LOOP [MCR4] = 1), this bit is equal to the MCR
bit 0 (DTR#). Ext. R
6 Complement of the ring indicator (RI#) input
When the ACE is in the diagnostic test mode
(LOOP [MCR4] = 1), this bit is equal to the MCR
bit 2 (OUT1#). Not supported. Ext. R
7 Complement of the data carrier detect
(DCD#) input
When the ACE is in the diagnostic test mode
(LOOP [MCR4] = 1), this bit is equal to the MCR
bit 3 (OUT2#). Not supported. Ext. R
Table 7-54 Modem Status Register (MSR) (continued)
IO Address: Base +6
Bit # Description Default Access