Artesyn iVPX7225 Installation and Use (April 2015) - Manual (Page 164)

FPGA Registers
iVPX7225 Installation and Use (6806800S11C) 145
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Table 7-56 Divisor Latch LSB Register (DLL), if DLAB=1
IO Address: Base
Bit # Description Default Access
7:0 Division Latch LSB (DLL) Cold Reset: 0 R/W
Table 7-57 Divisor Latch MSB Register (DLM), if DLAB=1
IO Address: Base +1
Bit # Description Default Access
7:0 Divisor Latch MSB (DLM) Cold Reset: 0 R/W
Table 7-58 Logical Device 0x74 Reserved Register
Index Address: Base 0x74
Bit # Description Default Access
7:0 Reserved 0x04 LPC:R
Table 7-59 Logical Device 0x75 Reserved Register
Index Address: Base 0x75
Bit # Description Default Access
7:0 Reserved 0x04 LPC:R
Table 7-60 Logical Device 0xF0 Reserved Register
Index Address: 0xF0
Bit # Description Default Access
7:0 Reserved 0 LPC: R