Artesyn iVPX7225 Installation and Use (April 2015) - Manual (Page 134)

FPGA Registers
iVPX7225 Installation and Use (6806800S11C) 115
7.1.20 PCIE Switch Control and Status 1 Register - 0x18
1 Current Flash Selection - RO RO
0: Boot flash 0 is selected.
1: Boot flash 1 is selected.
Note: Current FLASH selected is
indicated only when Boot Flash
Programming Enable is set
(enabled).
7:2 Reserved 0 RO RO
Table 7-19 Boot Control and Status 2 Register - 0x17 (continued)
Bit # Description Default LPC Access I2C Access
Table 7-20 PCIE Switch Control and Status 1 Register - 0x18
Bit # Description Default LPC Access I2C Access
1:0 Upstream Port Select 0x0 R/W -
00: Port 0 selected
01: Port 1 selected
10: Port 2 selected
11: Port 3 selected
3:2 Non-transparent Upstream Port
Select 0x1 R/W -
00: Port 0 selected
01: Port 1 selected
10: Port 2 selected
11: Port 3 selected
5:4 Port Configuration Select 0x1 R/W -
00: x4 x4 x4 x4
01: x8 x4 x4
10: x8 x4 x4
11: Reserved