Artesyn iVPX7225 Installation and Use (April 2015) - Manual (Page 136)

FPGA Registers
iVPX7225 Installation and Use (6806800S11C) 117
7.1.22 CPU Package Temperature Reading Register - 0x1C
7.1.23 IPMC Inlet Temperature Sensor Status Register - 0x1D
5 NT Reset Output Status Ext. RO -
0: PLX bridge NT reset is asserted
1: PLX bridge NT reset is de-asserted
6 FPGA SMI# Interrupt Request 1 R/W -
0: Interrupt is requested
1: Interrupt is not requested
7 1 KHz Clock Source Select 1 R/W -
0: 25 MHz selected to create 1kHz clock.
1: 2KHz selected to create 1Khz clock.
Table 7-21 PCIE Switch Control and Status 2 Register - 0x19 (continued)
Bit # Description Default LPC Access I2C Access
Table 7-22 CPU Package Temperature Reading Register - 0x1C
Bit # Description Default LPC Access I2C Access
7:0 CPU Package Temperature Reading 0x00 R/W RO
In hexadecimal value
Table 7-23 IPMC Inlet Temperature Sensor Status Register - 0x1D
Bit # Description Default LPC Access I2C Access
0 Reserved 0 RO R/W
1 Reserved 1 RO R/W
2 Reserved 0 RO R/W
3 Reserved 0 RO R/W