Address state, Address, Function – Fluke Biomedical 942A-200L-M4 User Manual

Page 23

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Theory of Operation

Main Circuit Board

2

2-9

Table 2-3. U1 Outputs

Address State

A8 A7 A6 A5

Address

Function

0 0 0 0

4000 Register

Select

0 0 0 1

4020 Bargraph

0 0 1 0

4040 ACIA

(Communication

Interface)

0 0 1 1

4060 SCA

(Analyzer)

0 1 0 0

4080

GPIB (General Purpose Interface
Bus)

0 1 0 1

40A0 (Spare)

0 1 1 0

40C0 (Spare)

0 1 1 1

40E0 (Spare)

Address 4000 is further decoded by the write register decoder (U2) and the read register decoder (U34).
The bargraph output, address 4020, is further decoded by U5. The remaining output address (4040
through 40E0) is provided to the optional interface connector for use by external option circuit boards.

PROM

The Programmable Read Only Memory is typically a 27256 that is a UV erasable 32K x 8-bit PROM. U23,
which responds to address 8000-FFFF, is always present. U23 contains the operating program for the
UDR (firmware). Jumper JP2 is normally set from 2 - 3. By setting JP2 from 2 - 3, A14 is applied to pin
27 of U23 that allows the use of a 27256 PROM (32K x 8).

RAM

Dynamic Random Access Memories (U21, U22) are utilized for temporary data storage. U21 J that
responds to address 0000-1FFF (8K x 8-bit) is always present. U22, which responds to address 2000-
3FFF, is an option. Data stored in the RAM is lost on power down.

E

2

Sixteen (16) monitor specific, operator entered setpoints are stored in 64 bytes of electrically erasable

memory (E2). U33 provides storage for the setpoints (256 bytes max.). The 16 setpoints are loaded
serially into PROM memory (U23) upon power up. U35 is an 8-Bit control register for the setpoints.

Read -Write Cycles

A read cycle is performed by sequencing /RAM 0000 and /RAM READ, while /RAM WRITE is held high
(inactive). The address (A0 - A12) are latched by the failing edge of /RAM 0000. Data becomes valid
approximately 250 ns later.

A write cycle is performed by sequencing /RAM 0000 and /RAM WRITE, while holding /RAM READ high
(inactive). Identical to the read cycle, the address (A0 - A12) is latched by the falling edge of /RAM 0000.
Data is stored into RAM on the failing edge of /RAM WRITE.

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