Avago Technologies LSI53C825AE - Manual (Page 10)

x Contents
6.5 PCI and External Memory Interface Timing 6-44
6.6 SCSI Timing Diagrams 6-45
6.7 Package Drawings 6-52
Appendix A Register Summary
Appendix B External Memory Interface Diagram Examples
Index
Customer Feedback
Figures
1.1 LSI53C825A External Memory Interface 1-9
1.2 LSI53C825A Chip Block Diagram 1-10
2.1 DMA FIFO Sections 2-23
2.2 LSI53C825A Host Interface Data Paths 2-27
2.3 LSI53C825A Differential Wiring Diagram 2-31
2.4 Regulated Termination 2-32
2.5 Determining the Synchronous Transfer Rate 2-35
2.6 Block Move and Chained Block Move Instructions 2-45
3.1 LSI53C825A Pin Diagram 3-2
3.2 LSI53C825AJ Pin Diagram 3-3
3.3 LSI53C825A Functional Signal Grouping 3-5
5.1 SCRIPTS Overview 5-5
5.2 Block Move Instruction Register 5-8
5.3 I/O Instruction Register 5-17
5.4 Read/Write Instruction Register 5-25
5.5 Transfer Control Instruction 5-31
5.6 Memory Move Instruction 5-39
5.7 Load and Store Instruction Format 5-43
6.1 Rise and Fall Time Test Conditions 6-9
6.2 SCSI Input Filtering 6-9
6.3 Hysteresis of SCSI Receivers 6-9
6.4 Input Current as a Function of Input Voltage 6-10
6.5 Output Current as a Function of Output Voltage 6-10