Avago Technologies LSI53C825AE - Manual (Page 195)

Block Move Instructions 5-11
Initiator Mode
In Target mode, the Opcode bit defines the following
operations:
These instructions perform the following steps:
1. The LSI53C825A verifies that it is connected to the
SCSI bus as an Initiator before executing this
instruction.
2. The LSI53C825A waits for an unserviced phase to
occur. An unserviced phase is any phase (with SREQ/
asserted) for which the LSI53C825A has not yet
transferred data by responding with a SACK/.
3. The LSI53C825A compares the SCSI phase bits in
the DMA Command (DCMD) register with the latched
SCSI phase lines stored in the SCSI Status One
(SSTAT1) register. These phase lines are latched
when SREQ/ is asserted.
4. If the SCSI phase bits match the value stored in the
SCSI SCSI Status One (SSTAT1) register, the
LSI53C825A transfers the number of bytes specified
in the
DMA Byte Counter (DBC) register starting at
the address pointed to by the DMA Next Address
(DNAD) register. If the opcode bit is cleared and a
data transfer ends on an odd byte boundary, the
LSI53C825A stores the last byte in the
SCSI Wide
Residue (SWIDE) register during a receive operation,
or in the SCSI Output Control Latch (SOCL) register
during a send operation. This byte is combined with
the first byte from the subsequent transfer so that a
wide transfer can complete.
OPC Instruction Defined
0 CHMOV
1 MOVE