Avago Technologies LSI53C825AE - Manual (Page 25)

LSI53C825A/825AE PCI to SCSI I/O Processor 2-1
Chapter 2
Functional Description
Chapter 2 is divided into the following sections:
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Section 2.1, “PCI Addressing”
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Section 2.2, “SCSI Functional Description”
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Section 2.3, “External Memory Interface”
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Section 2.4, “PCI Cache Mode”
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Section 2.5, “Power Management”
2.1 PCI Addressing
There are three physical PCI-defined address spaces:
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PCI Configuration Space
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I/O Space
•
Memory Space
2.1.1 Configuration Space
Configuration space is a contiguous 256 x 8-bit set of addresses
dedicated to each “slot” or “stub” on the bus. Decoding C_BE/[3:0]
determines if a PCI cycle is intended to access configuration register
space. The IDSEL bus signal is a “chip select” that allows access to the
configuration register space only. A configuration read/write cycle without
IDSEL is ignored. The eight lower order addresses are used to select a
specific 8-bit register. AD[10:8] are decoded as well, but they must be
zero or the LSI53C825A does not respond. According to the PCI
specification, AD[10:8] are to be used for multifunction devices. The host
processor uses the PCI configuration space to initialize the LSI53C825A.