Avago Technologies LSI53C825AE - Manual (Page 249)

PCI and External Memory Interface Timing Diagrams 6-21
Figure 6.13 External Memory Read (Cont.)
CLK
(Driven by System)
PAR
(Driven by Master-Addr;
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C825A)
STOP/
(Driven by LSI53C825A)
DEVSEL/
(Driven by LSI53C825A)
AD/
(Driven by Master-Addr;
C_BE/
(Driven by Master)
FRAME/
(Driven by Master)
Data Driven by Memory)
11 12 13 14 15 16 17 18 19 20
LSI53C825A-Data)
LSI53C825A-Data)
MAD
(Addr driven by LSI53C825A ;
GPIO2_MAS2/
(Driven by LSI53C825A)
MAS0/
(Driven by LSI53C825A)
MCE/
(Driven by LSI53C825A)
MOE/
(Driven by LSI53C825A)
MWE/
(Driven by LSI53C825A)
t
3
t
2
t
2
t
15
21
t
3
Out
t
3
t
3
Data
In
t
19
t
17
t
14
t
16
MAS1/
(Driven by LSI53C825A)
Data
Out