Avago Technologies LSI53C825AE - Manual (Page 252)

6-24 Specifications
6.4.2 Initiator Timing
Figure 6.15 through Figure 6.20 describe LSI53C825A Initiator timing.
Figure 6.15 Nonburst Opcode Fetch
CLK
(Driven by System)
FRAME/
(Driven by LSI53C825A)
AD/
(Driven by LSI53C825A-
C_BE/
(Driven by LSI53C825A)
PAR/
(Driven by LSI53C825A-
IRDY/
(Driven by LSI53C825A)
TRDY/
(Driven by Target)
STOP/
(Driven by Target)
DEVSEL/
(Driven by Target)
Addr/ Target-Data)
Addr; Target-Data)
GNT/
(Driven by Arbiter)
REQ/
(Driven by LSI53C825A)
GPIO1_MASTER/
(Driven by LSI53C825A)
GPIO0_FETCH/
(Driven by LSI53C825A)
Addr
Out
Addr
Out
CMD BE BE CMD
t
1
t
2
t
3
t
10
t
8
t
7
t
9
t
4
t
6
t
5
t
1
t
1
t
1
t
2
t
2
t
2
t
3
t
3
t
3
t
3
t
3
Data
In
Data
In