Document Outline

• List of Sections
• Table of Contents
• General Description
• Section 2. Memory Map
• Section 3. Random-Access Memory (RAM)
• Section 4. Read-Only Memory (ROM)
• Section 5. Configuration Register (CONFIG)
• Section 6. Central Processor Unit (CPU)
• Section 7. System Integration Module (SIM)
• Section 8. Clock Generator Module (CGM)
• Section 9. Universal Serial Bus Module (USB)
• Section 10. Monitor ROM (MON)
• Section 11. Timer Interface Module (TIM)
• Section 12. I/O Ports
• Section 13. Computer Operating Properly (COP)
• Section 14. External Interrupt (IRQ)
• Section 15. Keyboard Interrupt Module (KBI)
• Section 16. Break Module (BREAK)
• Section 17. Preliminary Electrical Specifications
• Section 18. Mechanical Specifications
• List of Figures
• List of Tables
• Section 1. General Description
  • 1.1 Contents
  • 1.2 Introduction
  • 1.3 Features
  • 1.4 MCU Block Diagram
  • 1.5 Pin Assignments
    • 1.5.1 Quad Flat Pack (QFP) Package
    • 1.5.2 Power Supply Pins (VDDA, VSSA, VDD1, VSS1, VDD2, and VSS2)
    • 1.5.3 Oscillator Pins (OSC1 and OSC2)
    • 1.5.4 External Reset Pin (RST)
    • 1.5.5 External Interrupt Pin (IRQ1/VPP)
    • 1.5.6 USB Data Pins (DPLUS0-DPLUS4 and DMINUS0-DMINUS4)
    • 1.5.7 Voltage Regulator Out (REGOUT)
    • 1.5.8 Port A Input/Output (I/O) Pins (PTA7-PTA0)
    • 1.5.9 Port B I/O Pins (PTB7-PTB0)
    • 1.5.10 Port C I/O Pins (PTC4-PTC0)
    • 1.5.11 Port D I/O Pins (PTD7/KBD7-PTD0/KBD0)
    • 1.5.12 Port E I/O Pins (PTE4, PTE3/KBE3, PTE2/KBE2/TCH1, PTE1/KBE1/TCH0, PTE0/KBE0/TCLK)
    • 1.5.13 Port F I/O Pins (PTF7/KBF7-PTF0/KBF0)
• Section 2. Memory Map
  • 2.1 Contents
  • 2.2 Introduction
  • 2.3 I/O Section
  • 2.4 Monitor ROM
• Section 3. Random-Access Memory (RAM)
  • 3.1 Contents
  • 3.2 Introduction
  • 3.3 Functional Description
• Section 4. Read-Only Memory (ROM)
  • 4.1 Contents
  • 4.2 Introduction
  • 4.3 Functional Description
• Section 5. Configuration Register (CONFIG)
  • 5.1 Contents
  • 5.2 Introduction
  • 5.3 Functional Description
• Section 6. Central Processor Unit (CPU)
  • 6.1 Contents
  • 6.2 Introduction
  • 6.3 Features
  • 6.4 CPU Registers
    • 6.4.1 Accumulator (A)
    • 6.4.2 Index Register (H:X)
    • 6.4.3 Stack Pointer (SP)
    • 6.4.4 Program Counter (PC)
    • 6.4.5 Condition Code Register (CCR)
  • 6.5 Arithmetic/Logic Unit (ALU)
• Section 7. System Integration Module (SIM)
  • 7.1 Contents
  • 7.2 Introduction
  • 7.3 SIM Bus Clock Control and Generation
    • 7.3.1 Bus Timing
    • 7.3.2 Clock Start-Up from POR
    • 7.3.3 Clocks in Stop Mode and Wait Mode
  • 7.4 Reset and System Initialization
    • 7.4.1 External Pin Reset
    • 7.4.2 Active Resets from Internal Sources
      • 7.4.2.1 Power-On Reset
      • 7.4.2.2 Computer Operating Properly (COP) Reset
      • 7.4.2.3 Illegal Opcode Reset
      • 7.4.2.4 Illegal Address Reset
      • 7.4.2.5 Universal Serial Bus Reset
  • 7.5 SIM Counter
    • 7.5.1 SIM Counter During Power-On Reset
    • 7.5.2 SIM Counter During Stop Mode Recovery
    • 7.5.3 SIM Counter and Reset States
  • 7.6 Exception Control
    • 7.6.1 Interrupts
      • 7.6.1.1 Hardware Interrupts
      • 7.6.1.2 SWI Instruction
    • 7.6.2 Interrupt Status Registers
      • 7.6.2.1 Interrupt Status Register 1
      • 7.6.2.2 Interrupt Status Register 2
      • 7.6.2.3 Interrupt Status Register 3
    • 7.6.3 Reset
    • 7.6.4 Break Interrupts
    • 7.6.5 Status Flag Protection in Break Mode
  • 7.7 Low-Power Modes
    • 7.7.1 Wait Mode
    • 7.7.2 Stop Mode
  • 7.8 SIM Registers
    • 7.8.1 Break Status Register (BSR)
    • 7.8.2 Reset Status Register (RSR)
    • 7.8.3 Break Flag Control Register (BFCR)
• Section 8. Clock Generator Module (CGM)
  • 8.1 Contents
  • 8.2 Introduction
  • 8.3 Features
  • 8.4 Functional Description
    • 8.4.1 Crystal Oscillator Circuit
    • 8.4.2 Phase-Locked Loop Circuit (PLL)
    • 8.4.3 PLL Circuits
    • 8.4.4 Acquisition and Tracking Modes
    • 8.4.5 Manual and Automatic PLL Bandwidth Modes
    • 8.4.6 Programming the PLL
    • 8.4.7 Special Programming Exceptions
    • 8.4.8 Base Clock Selector Circuit
    • 8.4.9 CGM External Connections
  • 8.5 I/O Signals
    • 8.5.1 Crystal Amplifier Input Pin (OSC1)
    • 8.5.2 Crystal Amplifier Output Pin (OSC2)
    • 8.5.3 External Filter Capacitor Pin (CGMXFC)
    • 8.5.4 PLL Analog Power Pin (VDDA)
    • 8.5.5 PLL Analog Ground Pin (VSSA)
    • 8.5.6 Buffered Crystal Clock Output (CGMVOUT)
    • 8.5.7 CGMVSEL
    • 8.5.8 Oscillator Enable Signal (SIMOSCEN)
    • 8.5.9 Crystal Output Frequency Signal (CGMXCLK)
    • 8.5.10 CGM Base Clock Output (CGMOUT)
    • 8.5.11 CGM CPU Interrupt (CGMINT)
  • 8.6 CGM Registers
    • 8.6.1 PLL Control Register (PCTL)
    • 8.6.2 PLL Bandwidth Control Register (PBWC)
    • 8.6.3 PLL Multiplier Select Registers (PMSH:PMSL)
    • 8.6.4 PLL Reference Divider Select Register (PRDS)
  • 8.7 Interrupts
  • 8.8 Special Modes
    • 8.8.1 Wait Mode
    • 8.8.2 CGM During Break Interrupts
  • 8.9 Acquisition/Lock Time Specifications
    • 8.9.1 Acquisition/Lock Time Definitions
    • 8.9.2 Parametric Influences on Reaction Time
    • 8.9.3 Choosing a Filter Capacitor
    • 8.9.4 Reaction Time Calculation
• Section 9. Universal Serial Bus Module (USB)
  • 9.1 Contents
  • 9.2 Features
  • 9.3 Overview
  • 9.4 I/O Register Description of the HUB function
    • 9.4.1 USB HUB Root Port Control Register (HRPCR)
    • 9.4.2 USB HUB Downstream Port Control Register (HDP1CR-HDP4CR)
    • 9.4.3 USB SIE Timing Interrupt Register (SIETIR)
    • 9.4.4 USB SIE Timing Status Register (SIETSR)
    • 9.4.5 USB HUB Address Register (HADDR)
    • 9.4.6 USB HUB Interrupt Register 0 (HIR0)
    • 9.4.7 USB HUB Control Register 0 (HCR0)
    • 9.4.8 USB HUB Endpoint1 Control & Data Register (HCDR)
    • 9.4.9 USB HUB Status Register (HSR)
    • 9.4.10 USB HUB Endpoint 0 Data Registers 0-7 (HE0D0-HE0D7)
  • 9.5 I/O Register Description of the Embedded Device Function
    • 9.5.1 USB Embedded Device Address Register (DADDR)
    • 9.5.2 USB Embedded Device Interrupt Register 0 (DIR0)
    • 9.5.3 USB Embedded Device Interrupt Register 1 (DIR1)
    • 9.5.4 USB Embedded Device Control Register 0 (DCR0)
    • 9.5.5 USB Embedded Device Control Register 1 (DCR1)
    • 9.5.6 USB Embedded Device Status Register (DSR)
    • 9.5.7 USB Embedded Device Control Register 2 (DCR2)
    • 9.5.8 USB Embedded Device Endpoint 0 Data Registers (DE0D0-DE0D7)
    • 9.5.9 USB Embedded Device Endpoint 1/2 Data Registers (DE1D0-DE1D7)
• Section 10. Monitor ROM (MON)
  • 10.1 Contents
  • 10.2 Introduction
  • 10.3 Features
  • 10.4 Functional Description
    • 10.4.1 Entering Monitor Mode
    • 10.4.2 Data Format
    • 10.4.3 Echoing
    • 10.4.4 Break Signal
    • 10.4.5 Commands
    • 10.4.6 Baud Rate
• Section 11. Timer Interface Module (TIM)
  • 11.1 Contents
  • 11.2 Introduction
  • 11.3 Features
  • 11.4 Functional Description
    • 11.4.1 TIM Counter Prescaler
    • 11.4.2 Input Capture
    • 11.4.3 Output Compare
      • 11.4.3.1 Unbuffered Output Compare
      • 11.4.3.2 Buffered Output Compare
    • 11.4.4 Pulse Width Modulation (PWM)
      • 11.4.4.1 Unbuffered PWM Signal Generation
      • 11.4.4.2 Buffered PWM Signal Generation
      • 11.4.4.3 PWM Initialization
  • 11.5 Interrupts
  • 11.6 Wait Mode
  • 11.7 TIM During Break Interrupts
  • 11.8 I/O Signals
    • 11.8.1 TIM Clock Pin (PTE0/TCLK)
    • 11.8.2 TIM Channel I/O Pins (PTE1/TCH0:PTE2/TCH1)
  • 11.9 I/O Registers
    • 11.9.1 TIM Status and Control Register (TSC)
    • 11.9.2 TIM Counter Registers (TCNTH:TCNTL)
    • 11.9.3 TIM Counter Modulo Registers (TMODH:TMODL)
    • 11.9.4 TIM Channel Status and Control Registers (TSC0:TSC1)
    • 11.9.5 TIM Channel Registers (TCH0H/L-TCH1H/L)
• Section 12. I/O Ports
  • 12.1 Contents
  • 12.2 Introduction
  • 12.3 Port A
    • 12.3.1 Port A Data Register (PTA)
    • 12.3.2 Data Direction Register A (DDRA)
  • 12.4 Port B
    • 12.4.1 Port B Data Register (PTB)
    • 12.4.2 Data Direction Register B (DDRB)
  • 12.5 Port C
    • 12.5.1 Port C Data Register (PTC)
    • 12.5.2 Data Direction Register C (DDRC)
  • 12.6 Port D
    • 12.6.1 Port D Data Register (PTD)
    • 12.6.2 Data Direction Register D (DDRD)
  • 12.7 Port E
    • 12.7.1 Port E Data Register (PTE)
    • 12.7.2 Data Direction Register E (DDRE)
    • 12.7.3 Port-E Optical Interface Enable Register
  • 12.8 Port F
    • 12.8.1 Port F Data Register (PTF)
    • 12.8.2 Data Direction Register F (DDRF)
  • 12.9 Port Options
    • 12.9.1 Port Option Control Register (POC)
• Section 13. Computer Operating Properly (COP)
  • 13.1 Contents
  • 13.2 Introduction
  • 13.3 Functional Description
  • 13.4 I/O Signals
    • 13.4.1 CGMXCLK
    • 13.4.2 COPCTL Write
    • 13.4.3 Power-On Reset
    • 13.4.4 Internal Reset
    • 13.4.5 Reset Vector Fetch
    • 13.4.6 COPD (COP Disable)
    • 13.4.7 COPRS (COP Rate Select)
  • 13.5 COP Control Register (COPCTL)
  • 13.6 Interrupts
  • 13.7 Monitor Mode
  • 13.8 Low-Power Modes
    • 13.8.1 Wait Mode
    • 13.8.2 Stop Mode
  • 13.9 COP Module During Break Mode
• Section 14. External Interrupt (IRQ)
  • 14.1 Contents
  • 14.2 Introduction
  • 14.3 Features
  • 14.4 Functional Description
    • 14.4.1 IRQ1/Vpp Pin
  • 14.5 IRQ Module During Break Interrupts
  • 14.6 IRQ Status and Control Register (ISCR)
• Section 15. Keyboard Interrupt Module (KBI)
  • 15.1 Contents
  • 15.2 Introduction
  • 15.3 Features
  • 15.4 Port-D Keyboard Interrupt Block Diagram
    • 15.4.1 Port-D Keyboard Interrupt Functional Description
    • 15.4.2 Port-D Keyboard Initialization
    • 15.4.3 Port-D Keyboard Interrupt Registers
      • 15.4.3.1 Port-D Keyboard Status and Control Register:
      • 15.4.3.2 Port-D Keyboard Interrupt Enable Register
  • 15.5 Port-E Keyboard Interrupt Block Diagram
    • 15.5.1 Port-E Keyboard Interrupt Functional Description
    • 15.5.2 Port-E Keyboard Initialization
    • 15.5.3 Port-E Keyboard Interrupt Registers
      • 15.5.3.1 Port-E Keyboard Status and Control Register
      • 15.5.3.2 Port-E Keyboard Interrupt Enable Register
  • 15.6 Port-F Keyboard Interrupt Block Diagram
    • 15.6.1 Port-F Keyboard Interrupt Functional Description
    • 15.6.2 Port-F Keyboard Initialization
    • 15.6.3 Port-F Keyboard Interrupt Registers
      • 15.6.3.1 Port-F Keyboard Status and Control Register
      • 15.6.3.2 Port-F Keyboard Interrupt Enable Register
      • 15.6.3.3 Port-F Pull-up Enable Register
  • 15.7 Wait Mode
  • 15.8 Stop Mode
  • 15.9 Keyboard Module During Break Interrupts
• Section 16. Break Module (BREAK)
  • 16.1 Contents
  • 16.2 Introduction
  • 16.3 Features
  • 16.4 Functional Description
    • 16.4.1 Flag Protection During Break Interrupts
    • 16.4.2 CPU During Break Interrupts
    • 16.4.3 TIM During Break Interrupts
    • 16.4.4 COP During Break Interrupts
  • 16.5 Break Module Registers
    • 16.5.1 Break Status and Control Register (BRKSCR)
    • 16.5.2 Break Address Registers (BRKH and BRKL)
  • 16.6 Low-Power Modes
    • 16.6.1 Wait Mode
    • 16.6.2 Stop Mode
• Section 17. Preliminary Electrical Specifications
  • 17.1 Contents
  • 17.2 Introduction
  • 17.3 Absolute Maximum Ratings
  • 17.4 Functional Operating Range
  • 17.5 Thermal Characteristics
  • 17.6 DC Electrical Characteristics
  • 17.7 Control Timing
  • 17.8 Oscillator Characteristics
  • 17.9 USB DC Electrical Characteristics
  • 17.10 USB Low Speed Source Electrical Characteristics
  • 17.11 USB High Speed Source Electrical Characteristics
  • 17.12 HUB Repeater Electrical Characteristics
  • 17.13 USB Signaling Levels
  • 17.14 TImer Interface Module Characteristics
  • 17.15 Clock Generation Module Characteristics
    • 17.15.1 CGM Component Specifications
    • 17.15.2 CGM Electrical Specifications
    • 17.15.3 Acquisition/Lock Time Specifications
• Section 18. Mechanical Specifications
  • 18.1 Contents
  • 18.2 Introduction
  • 18.3 Plastic Quad Flat Pack (QFP)