Freescale Semiconductor MC68HC08KH12 - Manual (Page 193)

MC68HC(7)08KH12 — Rev. 1.1 Advance Information
Freescale Semiconductor 193
12.6.1 Port D Data Register (PTD)
The port D data register contains a data latch for each of the eight port D
pins.
PTD[7:0] — Port D Data Bits
These read/write bits are software programmable. Data direction of
each port D pin is under control of the corresponding bit in data
direction register D. Reset has no effect on port D data.
The port D pullups are automatically enabled if the respective pin is
configured as a keyboard interrupt. (See
15.4.1 Port-D Keyboard
Interrupt Functional Description .)
The port-D keyboard interrupt enable bits, KBDIE7—KBDIE0, in the
port-D keyboard interrupt enable register (KBDIER), enable the port D
pins as external interrupt pins.
See Section 15. Keyboard Interrupt
Module (KBI) .
12.6.2 Data Direction Register D (DDRD)
Data direction register D determines whether each port D pin is an input
or an output. Writing a logic one to a DDRD bit enables the output buffer
for the corresponding port D pin; a logic zero disables the output buffer.
Address: $0003
Bit 7 6 5 4 3 2 1 Bit 0
Read:
PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0
Write:
Reset: Unaffected by reset
Alternate
Function:
KBD7 KBD6 KBD5 KBD4 KBD3 KBD2 KBD1 KBD0
Figure 12-10. Port D Data Register (PTD)