Freescale Semiconductor MC68HC08KH12 - Manual (Page 80)

Advance Information MC68HC(7)08KH12 — Rev. 1.1
80 Freescale Semiconductor
below. Both STOP and WAIT clear the interrupt mask (I) in the condition
code register, allowing interrupts to occur.
7.7.1 Wait Mode
In wait mode, the CPU clocks are inactive while the peripheral clocks
continue to run.
Figure 7-15 shows the timing for wait mode entry.
A module that is active during wait mode can wake up the CPU with an
interrupt if the interrupt is enabled. Stacking for the interrupt begins one
cycle after the WAIT instruction during which the interrupt occurred. In
wait mode, the CPU clocks are inactive. Refer to the wait mode
subsection of each module to see if the module is active or inactive in
wait mode. Some modules can be programmed to be active in wait
mode.
Wait mode can also be exited by a reset or break. A break interrupt
during wait mode sets the SIM break stop/wait bit, SBSW, in the break
status register (BSR). If the COP disable bit, COPD, in the mask option
register is logic zero, then the computer operating properly module
(COP) is enabled and remains active in wait mode.
Figure 7-15. Wait Mode Entry Timing
Figure 7-16 and Figure 7-17 show the timing for WAIT recovery.
WAIT ADDR + 1 SAME SAME IAB
IDB PREVIOUS DATA NEXT OPCODE SAME
WAIT ADDR
SAME
R/W
NOTE: Previous data can be operand data or the WAIT opcode, depending on the
last instruction.