Freescale Semiconductor MC68HC08KH12 - Manual (Page 69)

MC68HC(7)08KH12 — Rev. 1.1 Advance Information
Freescale Semiconductor 69
Figure 7-7. POR Recovery
7.4.2.2 Computer Operating Properly (COP) Reset
An input to the SIM is reserved for the COP reset signal. The overflow of
the COP counter causes an internal reset and sets the COP bit in the
reset status register (RSR). The SIM actively pulls down the RST pin for
all internal reset sources.
To prevent a COP module timeout, write any value to location $FFFF.
Writing to location $FFFF clears the COP counter and stages 12 through
5 of the SIM counter. The SIM counter output, which occurs at least
every 2
12
– 2
4
CGMXCLK cycles, drives the COP counter. The COP
should be serviced as soon as possible out of reset to guarantee the
maximum amount of time before the first timeout.
The COP module is disabled if the RST pin or the IRQ1/V
PP
pin is held
at V
DD
+ V
HI
while the MCU is in monitor mode. The COP module can
be disabled only through combinational logic conditioned with the high
voltage signal on the RST or the IRQ1/V
PP
pin. This prevents the COP
from becoming disabled as a result of external noise. During a break
state, V
DD
+ V
HI
on the RST pin disables the COP module.
PORRST
OSC1
CGMXCLK
CGMOUT
RST
IAB
4096
CYCLES
32
CYCLES
32
CYCLES
$FFFE $FFFF