Freescale Semiconductor MC68HC08KH12 - Manual (Page 81)

MC68HC(7)08KH12 — Rev. 1.1 Advance Information
Freescale Semiconductor 81
Figure 7-16. Wait Recovery from Interrupt or Break
Figure 7-17. Wait Recovery from Internal Reset
7.7.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are
disabled. An interrupt request from a module can cause an exit from stop
mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the oscillator signals (CGMOUT and CGMXCLK) in
stop mode, stopping the CPU and peripherals. Stop recovery time is
selectable using the SSREC bit in the configuration register (CONFIG).
If SSREC is set, stop recovery is reduced from the normal delay of 4096
CGMXCLK cycles down to 32. This is ideal for applications using canned
oscillators that do not require long startup times from stop mode.
NOTE: External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
$6E0C $6E0B $00FF $00FE $00FD $00FC
$A6 $A6 $01 $0B $6E $A6
IAB
IDB
EXITSTOPWAIT
NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt
IAB
IDB
RST
$A6 $A6
$6E0B RST VCT H RST VCT L
$A6
CGMXCLKCGMXCLK
32
Cycles
32
Cycles