Freescale Semiconductor MC68HC08KH12 - Manual (Page 242)

Advance Information MC68HC(7)08KH12 — Rev. 1.1
242 Freescale Semiconductor
16.3 Features
Features of the break module include the following:
• Accessible I/O Registers during the Break Interrupt
• CPU-Generated Break Interrupts
• Software-Generated Break Interrupts
• COP Disabling during Break Interrupts
16.4 Functional Description
When the internal address bus matches the value written in the break
address registers, the break module issues a breakpoint signal (BKPT)
to the SIM. The SIM then causes the CPU to load the instruction register
with a software interrupt instruction (SWI) after completion of the current
CPU instruction. The program counter vectors to $FFFC and $FFFD
($FEFC and $FEFD in monitor mode).
The following events can cause a break interrupt to occur:
• A CPU-generated address (the address in the program counter)
matches the contents of the break address registers.
• Software writes a logic one to the BRKA bit in the break status and
control register.
When a CPU generated address matches the contents of the break
address registers, the break interrupt begins after the CPU completes its
current instruction. A return from interrupt instruction (RTI) in the break
routine ends the break interrupt and returns the MCU to normal
operation.
Figure 16-1 shows the structure of the break module.