3 pll multiplier select registers (pmsh:pmsl), Pll multiplier select registers (pmsh:pmsl), 3 pll – Freescale Semiconductor MC68HC08KH12 User Manual
Page 105: Multiplier select registers (pmsh:pmsl)
MC68HC(7)08KH12
—
Rev. 1.1
Advance Information
Freescale Semiconductor
105
logic zero and has no meaning. The write one function of this bit is
reserved for test, so this bit must always be written a zero. Reset
clears the LOCK bit.
1 = VCO frequency correct or locked
0 = VCO frequency incorrect or unlocked
ACQ — Acquisition Mode Bit
When the AUTO bit is set, ACQ is a read-only bit that indicates
whether the PLL is in acquisition mode or tracking mode. When the
AUTO bit is clear, ACQ is a read/write bit that controls whether the
PLL is in acquisition or tracking mode.
In automatic bandwidth control mode (AUTO = 1), the last-written
value from manual operation is stored in a temporary location and is
recovered when manual operation resumes. Reset clears this bit,
enabling acquisition mode.
1 = Tracking mode
0 = Acquisition mode
8.6.3 PLL Multiplier Select Registers (PMSH:PMSL)
The PLL multiplier select registers contain the programming information
for the modulo feedback divider.
Address:
$003C
PMSH
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
MUL11
MUL10
MUL9
MUL8
Write:
Reset:
0
0
0
0
0
0
0
0
Address:
$003D
PMSL
Read:
MUL7
MUL6
MUL5
MUL4
MUL3
MUL2
MUL1
MUL0
Write:
Reset:
0
0
0
0
0
0
1
0
= Unimplemented
Figure 8-5. PLL Multiplier Select Registers (PMSH:PMSL)