Freescale Semiconductor MC68HC08KH12 - Manual (Page 209)

MC68HC(7)08KH12 — Rev. 1.1 Advance Information
Freescale Semiconductor 209
The COP counter is a free-running 6-bit counter preceded by the 12-bit
SIM counter. If not cleared by software, the COP counter overflows and
generates an asynchronous reset after 2
18
– 2
4
or 2
13
– 2
4
CGMXCLK
cycles, depending on the setting of the COP rate select bit, COPRS, in
the configuration register. With a 2
18
– 2
4
CGMXCLK cycle overflow
option, a 6MHz crystal gives a COP timeout period of 43.688ms. Writing
any value to location $FFFF before an overflow occurs prevents a COP
reset by clearing the COP counter and stages 12 through 5 of the SIM
counter.
NOTE: Service the COP immediately after reset and before entering or after
exiting stop mode to guarantee the maximum time before the first COP
counter overflow.
A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the
COP bit in the reset status register (RSR)
(see 7.8.2 Reset Status
Register (RSR) ).
NOTE: Place COP clearing instructions in the main program and not in an
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly.
13.4 I/O Signals
The following paragraphs describe the signals shown in Figure 13-1 .
13.4.1 CGMXCLK
CGMXCLK is the crystal oscillator output signal. CGMXCLK frequency
is equal to the crystal frequency.
13.4.2 COPCTL Write
Writing any value to the COP control register (COPCTL) (see 13.5 COP
Control Register (COPCTL) ) clears the COP counter and clears bits 12
through 4 of the SIM counter. Reading the COP control register returns
the low byte of the reset vector.