Freescale Semiconductor MC68HC08KH12 - Manual (Page 131)

MC68HC(7)08KH12 — Rev. 1.1 Advance Information
Freescale Semiconductor 131
TPSIZ3-TPSIZ0 — HUB Endpoint 0 Transmit Data Packet Size
These read/write bits store the number of transmit data bytes for the
next IN token request for HUB Endpoint 0. These bits are cleared by
reset.
9.4.8 USB HUB Endpoint1 Control & Data Register (HCDR)
STALL1 — HUB Endpoint 1 Force Stall Bit
This read/write bit causes HUB Endpoint 1 to return a STALL
handshake when polled by the host. Reset clears this bit.
1 = Send STALL handshake
0 = Default
PNEW — Port New Status Change
This read/write bit enables a transmit to occur when the USB Host
controller sends an IN token to HUB Endpoint 1. Software should set
this bit when there is any status change on the downstream ports,
embedded device or hub. It must be cleared by software when there
is no status change needs to be reported to the host through the
Endpoint1. If this bit is 0, a NAK handshake will be returned for next
IN token for HUB Endpoint 1. Reset clears this bit.
1 = Port status change bit is ready to be sent.
0 = Port status does not change. Respond with NAK.
Address: $005C
Bit 7 6 5 4 3 2 1 Bit 0
Read:
STALL1 PNEW PCHG5 PCHG4 PCHG3 PCHG2 PCHG1 PCHG0
Write:
Reset: 0 0 0 0 0 0 0 0
Figure 9-9. USB HUB Control Register 1 (HCR1)