Freescale Semiconductor MC68HC08KH12 User Manual
Page 112
Advance Information
MC68HC(7)08KH12
—
Rev. 1.1
112
Freescale Semiconductor
an initial frequency error, (f
DES
– f
ORIG
)/f
DES
, of not more than
±
100
percent.
NOTE:
The inverse proportionality between the lock time and the reference
frequency.
In automatic bandwidth control mode, the acquisition and lock times are
quantized into units based on the reference frequency. (See
Manual and Automatic PLL Bandwidth Modes
clock cycles, n
ACQ
, is required to ascertain that the PLL is within the
tracking mode entry tolerance,
∆
TRK
, before exiting acquisition mode. A
certain number of clock cycles, n
TRK
, is required to ascertain that the PLL
is within the lock mode entry tolerance,
∆
LOCK
. Therefore, the acquisition
time, t
ACQ
, is an integer multiple of n
ACQ
/f
RDV
, and the acquisition to lock
time, t
AL
, is an integer multiple of n
TRK
/f
RDV
.
In manual mode, it is usually necessary to wait considerably longer than
t
LOCKMAX
before selecting the PLL clock (See
.), because the factors described in
may slow the lock time considerably.
Automatic bandwidth mode is recommended for most users.
t
ACQ
V
DDA
f
RDV
-------------
8
K
ACQ
-------------
=
t
AL
V
DDA
f
RDV
-------------
4
K
TRK
------------
=
t
LOCKMAX
t
ACQ
t
AL
256t
VRDV
+
+
=