Freescale Semiconductor MC68HC08KH12 - Manual (Page 141)

MC68HC(7)08KH12 — Rev. 1.1 Advance Information
Freescale Semiconductor 141
1 = Transmit on Endpoint 1 or Endpoint 2 of the embedded device
has occurred
0 = Transmit on Endpoint 1 or Endpoint 2 of the embedded device
has not occurred
TXD1IE — Embedded Device Endpoint 1/2 Transmit Interrupt Enable
This read/write bit enables the USB to generate CPU interrupt
requests when the shared Transmit Endpoint 1/2 interrupt flag bit of
the embedded device (TXD1F) becomes set. Reset clears the
TXD1IE bit.
1 = Transmit embedded device Endpoints 1 and 2 can generate a
CPU interrupt request
0 = Transmit embedded device Endpoints 1 and 2 cannot generate
a CPU interrupt request
TXD1FR — Embedded Device Endpoint 1/2 Transmit Flag Reset
Writing a logic 1 to this write only bit will clear the TXD1F bit if it is set.
Writing a logic 0 to TXD1FR has no effect. Reset clears this bit.
9.5.4 USB Embedded Device Control Register 0 (DCR0)
T0SEQ — Embedded Device Endpoint 0 Transmit Sequence Bit
This read/write bit determines which type of data packet (DATA0 or
DATA1) will be sent during the next IN transaction directed at
Endpoint 0. Toggling of this bit must be controlled by software. Reset
clears this bit.
Address: $004B
Bit 7 6 5 4 3 2 1 Bit 0
Read:
T0SEQ DSTALL0 TX0E RX0E TP0SIZ3 TP0SIZ2 TP0SIZ1 TP0SIZ0
Write:
Reset: 0 0 0 0 0 0 0 0
Figure 9-15. USB Embedded Device Control Register 0 (DCR0)