Freescale Semiconductor MC68HC08KH12 - Manual (Page 92)

Advance Information MC68HC(7)08KH12 — Rev. 1.1
92 Freescale Semiconductor
The operating range of the VCO is programmable for a wide range of
frequencies and for maximum immunity to external noise, including
supply and CGM/XFC noise. The VCO frequency is bound to a range
from roughly 40MHz to 56MHz, f
VRS
. Modulating the voltage on the
CGM/XFC pin changes the frequency within this range. By design, f
VRS
is tuned to a nominal center-of-range frequency of 48MHz.
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK.
CGMRCLK runs at a frequency, f
RCLK
, and is fed to the PLL through a
programmable modulo reference divider, which divides f
RCLK
by a factor
R. This feature allows frequency steps of higher resolution. The divider’s
output is the final reference clock, CGMRDV, running at a frequency
f
RDV
= f
RCLK
/R.
The VCO’s output clock, CLK, running at a frequency f
VCLK
is fed back
through a programmable prescale divider and a programmable modulo
divider. The prescaler divides the VCO clock by a power-of-two factor P
and the modulo divider reduces the VCO clock by a factor, N. The
dividers’ output is the VCO feedback clock, CGMVDV, running at a
frequency f
VDV
= f
VCLK
/(N
×
2
P
). (See 8.4.6 Programming the PLL for
more information.)
The phase detector then compares the VCO feedback clock, CGMVDV,
with the final reference clock, CGMRDV. A correction pulse is generated
based on the phase difference between the two signals. The loop filter
then slightly alters the DC voltage on the external capacitor connected
to CGM/XFC based on the width and direction of the correction pulse.
The filter can make fast or slow corrections depending on its mode,
described in
8.4.4 Acquisition and Tracking Modes . The value of the
external capacitor and the reference frequency determines the speed of
the corrections and the stability of the PLL.
The lock detector compares the frequencies of the VCO feedback clock,
CGMVDV, and the final reference clock, CGMRDV. Therefore, the
speed of the lock detector is directly proportional to the final reference
frequency, f
RDV
. The circuit determines the mode of the PLL and the lock
condition based on this comparison.