Freescale Semiconductor MC68HC08KH12 - Manual (Page 225)

MC68HC(7)08KH12 — Rev. 1.1 Advance Information
Freescale Semiconductor 225
3. Write to the ACKD bit in the keyboard status and control register
to clear any false interrupts.
4. Clear the IMASKD bit.
An interrupt signal on an edge-triggered pin can be acknowledged
immediately after enabling the pin. An interrupt signal on an edge- and
level-triggered interrupt pin must be acknowledged after a delay that
depends on the external load.
Another way to avoid a false interrupt for port-D:
1. Configure the keyboard pins as outputs by setting the appropriate
DDRD bits in data direction register D.
2. Write logic 1s to the appropriate port-D data register bits.
3. Enable the KBDI pins by setting the appropriate KBDIEx bits in the
keyboard interrupt enable register.
15.4.3 Port-D Keyboard Interrupt Registers
15.4.3.1 Port-D Keyboard Status and Control Register:
• Flags keyboard interrupt requests.
• Acknowledges keyboard interrupt requests.
• Masks keyboard interrupt requests.
• Controls keyboard interrupt triggering sensitivity.
Bits [7:4] — Not used
These read-only bits always read as logic 0s.
Address: $000C
Bit 7 6 5 4 3 2 1 Bit 0
Read: 0 0 0 0 KEYDF 0
IMASKD MODED
Write: ACKD
Reset: 0 0 0 0 0 0 0 0
= Unimplemented
Figure 15-2. Port-D Keyboard Status and Control Register (KBDSCR)